How to measure Vth of MOS transistor against his lenght in ADE

Draw schematic, like this:

Gate-source voltage V0 must be a half of Supply voltage (V1)

Steps for Cadence IC ver. 6
1. Choose DC analysis, check boxes Save DC Operation Point, Enabled and press OK.
2. Select test transistor and open his properties (Edit - Properties - Objects...), in string l (M) delete the value of lenght and write variable name (LL for example), press OK.
3. Open Calculator, select op, click on test transistor, in window OP Parameters for ... select vth from list box. Put the result expression from the Calculator to the Outputs (OP("/M0","vth") in my case)
4. Go to Parametric analysis and add range for LL (500n - 10u for example)
5. Run simulation

Steps for Cadence IC ver. 5
1. Choose DC analysis, check boxes Save DC Operation Point, Enabled and press OK.
2. Select test transistor and open his properties (Edit - Properties - Objects...), in string l (M) delete the value of lenght and write variable name (LL for example), press OK.
3. Choose value for variable LL in ADE
4. Run analysis
5. Open calculator, go to tab info, select op, choose our transistor, in window OP Parameters for ... select vth from list box. Put the result expression from the Calculator to the Outputs (OP("/M0","vth") in my case)
6. Go to Parametric analysis and add range for LL (500n - 10u for example)
7. Run parametric analysis.

Warnings on POWER and GROUND pins on LVS

When you have warnings during LVS check about power and ground pins like this:


Warning: #3 in pll_ref
WARNING: Invalid PATHCHK request "! POWER": no POWER nets present, operation aborted.


Warning: #4 in pll_ref
WARNING: Invalid PATHCHK request "GROUND && ! POWER": no POWER nets present, operation aborted.


Warning: #5 in pll_ref
WARNING: Invalid PATHCHK request "POWER && ! GROUND": no POWER nets present, operation aborted.


Warning: #6 in pll_ref
WARNING: Invalid PATHCHK request "! POWER && ! GROUND": no POWER nets present, operation aborted.

Go to Calibre - Run LVS - LVS Options - Supply and add names of power and ground pins of your scheme to the Power nets: and Ground nets: fields

Error code 4 "source not found" in Calibre LVS

If you have this error when run LVS it is mean that calibre can't create netlist of schematic. To solve this problem do the follow:

in CIW go File - Export - CDL. Choose your library, cell name and schematic view, define Run Directory (where you want to place netlist file, in my case "cal_log" dir) and name of the netlist like in Calibre LVS. Choose box Renetlist. And press Ok.


Go Calibre - Run LVS - Inputs - Netlist - Files:  Enter the name of created netlist or assure that name is present (with  .src.net extension). Remove check in box "Export from schematic viewer"

Problems with SUBCKT in Calibre LVS with TSMC90 technology

If you have a problem with resistors or other components like a

"Source netlist references but does not define (1) subckt: rppolywo" 


add SUBCKT netlist file "source_added" in this place:
Calibre - Run LVS - Inputs - Netlist - Files: add a string "source_added" (you must copy a file "source_added" in directory whith netlist file (directory "cal_log" in my case)

Case sensitivity of net and pin names in Calibre PEX

If you get warnings about pin names in Calibre PEX extraction, do the following:
Calibre - Run PEX - Pex Options - Include - check the box “Include SVRF Commands” and add this two strings in the command window:

SOURCE CASE YES
LAYOUT CASE YES

Now Calibre is sensitive to case of pins and net names in netlist and layout.

Check problem markers in Layout XL

If you want to check highlighted error markers in layout do the follow:
Verify - Markers - Explain